AD9577BCPZ

AD9577 provides a multioutput clock generator function, along with two on-chip phase-locked loop cores, PLL1 and PLL2, optimized for network clocking applications. The PLL designs are based on the Analog Devices, Inc., proven portfolio of high performance, low jitter frequency synthesizers to maximize network performance. The PLLs have I²C programmable output frequencies and formats. The fractional-N PLL can support spread spectrum clocking for reduced EMI radiated peak power. The first integer-N PLL section consists of a low noise phase frequency detector, a precision charge pump, a low phase noise voltage controlled oscillator, a programmable feedback divider, and two independently programmable output dividers. Application includes low jitter, low phase noise multioutput clock generator for data communications applications including Ethernet, fibre channel, SONET, SDH, PCI-e, SATA, PTN, OTN, ADC/DAC, and digital video, spread spectrum clocking.

• Fully integrated dual PLL/VCO cores, 1 integer-N and 1 fractional-N PLL
• Continuous frequency coverage from 11.2MHz to 200MHz
• PLL1 phase jitter (12KHz to 20MHz) is 460fs rms (typical)
• Integer-N mode is 470fs rms (typ), fractional-N mode is 660fs rms (typ)
• Input crystal or reference clock frequency, I²C programmable output frequencies
• Up to 4 LVDS/LVPECL or up to 8 LVCMOS output clocks, 1 CMOS buffered reference clock output
• Spread spectrum range from +0.1 to 0.5% (down spread)
• 2 pin-controlled frequency maps: margining, integrated loop filters
• RMS jitter (625MHz output) is 460fs rms (typ, 12KHz to 20MHz, Na = 100, Vx = 2, Dx = 2)
• 40 lead LFCSP-WQ package, operating temperature range from -40°C to +85°C

Merknader

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